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dmi 3110 a digital mac interface edition nov. 8, 1996 6251-381-2ds micronas intermetall micronas
dmi 3110 a micronas intermetall 2 contents page section title 4 1. introduction 4 2. functional description 4 2.1. clock generation 5 2.2. automatic gain control 5 2.3. clamping 5 2.4. a/d converter 5 2.5. pal encoder 5 2.6. teletext transcoder 5 2.7. osd formatter and insertion 5 2.8. luminance offset subtracter 5 2.9. equalization delay 6 2.10. 4:4:4 interpolation 6 2.11. matrix 6 2.12. d/a converters 6 2.13. i 2 c-bus interface 8 3. specifications 8 3.1. outline dimensions 8 3.2. pin connections and short descriptions 11 3.3. pin descriptions 12 3.4. pin configuration 13 3.5. pin circuits 14 3.6. electrical characteristics 14 3.6.1. absolute maximum ratings 14 3.6.2. recommended operating conditions 15 3.6.3. crystal oscillator (dco) characteristics (for tc09) 16 3.6.4. characteristics 19 4. programming 19 4.1. i 2 c-bus interface 22 4.2. general remarks 22 4.2.1. initialization 22 4.3. analog input 22 4.3.1. input select (34) 22 4.3.2. clamping enable (34) 22 4.3.3. automatic gain control (36) 22 4.3.4. baseband output code (34) 22 4.4. chrominance channel 22 4.4.1. chroma demultiplexer phase (5, 26) 23 4.4.2. chroma lowpass (5) 23 4.4.3. color component gain (6,7) 23 4.4.4. color burst (4) 23 4.4.5. color carrier gain (3) 23 4.5. luminance channel 23 4.5.1. luminance offset (26) 23 4.5.2. luminance lowpass filter (2) 23 4.5.3. luminance gain (2) 24 4.6. timing 24 4.6.1. horizontal pulses (1, 8 to 11, 17, 19)
dmi 3110 a micronas intermetall 3 contents, continued page section title 24 4.6.2. short vertical sync (15, 20, 21) 24 4.6.3. vertical pulses (12, 18) 24 4.6.4. delay for csync, luminance and rgb (13, 14, 27) 25 4.7. teletext transcoder (23, 30 to 33) 25 4.8. on-screen display (48 to 63) 25 4.9. rgb processing 28 5. data sheet history
dmi 3110 a micronas intermetall 4 dmi 3110 a digital mac interface 1. introduction the dmi 3110 a is a d2mac interface implemented in cmos technology and housed in a 68-pin plcc pack- age. it delivers analog rgb signals, a pal-coded com- posite video signal (cvbs) and separate pal-coded lu- minance and chrominance signals for svhs. also included is an 8-bit a/d converter for digitizing the ana- log d2mac signal and a digital interface to the interme- tall d2mac chip set. the main features are: 8-bit a/d converter with clamping and agc clock generation with digital pll teletext transcoding mac to pal (vbi) pal encoder with osd and teletext insertion 3 d/a converters for cvbs, y, c 3 d/a converters for rgb or yuv with osd insertion i 2 c-bus interface for communication with the ccu 2. functional description the following text describes the functions of the dmi. the descriptions refer to the block diagram. 2.1. clock generation the complete chip runs with a 20.25 mhz clock. this clock is produced by the clock generation circuitry. the clock generator comprises a 20.25 mhz crystal oscilla- tor that is digitally controlled within 150 ppm with 9-bit resolution. the frequency will be controlled by two switched capacitors. the input signal for the control loop is generated in the d2mac decoder ic. the clock output signal itself is fed to the d2mac chips. dma chips clock generation clamping and agc 8 bit adc reset circuit i 2 c-bus interface 4:4:4 interpola- tion osd insertion (yuv) osd inser- tion (pal) pal encoder matrix yuv rgb 3 dac y c cvbs 3 dac yuv or rgb 816 4 3 2 9 mac yuv osd mac data/sync csync pll clock 5 v gnd (rgb, fb) clamping y c r, v g, y b, u reset i 2 c-bus mac1 mac2 top ref. yuv rgb y 2 2 offset subtract teletext (vbi) trans coder osd formatter equal- ization delay u, v signal gnd cvbs fig. 21: dmi block diagram
dmi 3110 a micronas intermetall 5 2.2. automatic gain control the agc circuit controls the gain for the analog input signal and feeds the controlled signal to the following a/d converter. the input voltage can vary in the range from 0.5 v pp to 2 v pp (1 v pp 6 db). the amplitude of the a/d converter output signal will be measured in the d2mac decoder circuit and read from a central control unit (ccu) over the i 2 c-bus to calculate the gain control signal. the measurement will be done in line 624, there- fore the digital baseband input signal for the d2mac de- coder should not be influenced by other circuits during this line. the gain control itself is done by a digital gain controlled amplifier in front of the a/d converter. the gain range of 6 db is logarithmically scaled in 64 steps with a step size of 0.19 db. as the control algorithm is done by soft- ware in the ccu, features of the agc, such as histories and backlash functions can also be provided easily. 2.3. clamping the clamping circuit clamps the analog input signal to a fixed level. the offset value of the digital mac signal is measured in the d2mac decoder and the clamping sig- nal is fed to the dmi circuit as 4-bit pdm (pulse density modulated) signal. in the dmi a clamping current is gen- erated for the coupling capacitors at the mac inputs. for proper functioning of the clamping it is required to con- nect no circuit with an extra clamping function between the digital mac output of the dmi and the input of the d2mac decoder. 2.4. a/d converter the a/d converter is an 8-bit two-step flash converter which runs at 20.25 mhz. the output signal is purely binary-coded and is fed to the d2mac decoder. option- ally, the signal can be selected to become gray code for- mat. the reference voltage is internally generated and is connected to one pin for a decoupling capacitor. the a/d converter (and the d/a converters) are connected to extra 5v and ground pins for a supply with a separate low-noise supply voltage. the analog mac input signal must be ac-coupled over a coupling capacitor. 2.5. pal encoder the pal encoder receives the digital 4:2:2 component signal (yuv) from the d2mac decoder. the encoder is also connected to the on-screen display (osd) format- ter and to the teletext transcoder. these signals will be coded into a composite video signal in the pal standard. three d/a converters produce the composite video sig- nal, the chrominance signal and the luminance signal. 2.6. teletext transcoder the dmi can handle d2mac teletext signals trans- mitted in the vertical blanking interval (vbi). in the trans- coder, the teletext signal is extracted from the d2mac data signal. the data rate and signal timing are con- verted according to the wst teletext standard. teletext transcoding is active in tv lines 6 to 22 and 319 to 335 of the pal signal. thus not all lines that can carry tele- text in the d2mac standard (2 to 22 and 314 to 334) are transcoded. a generator in the transcoder generates the correct teletext bit frequency. a programmable window for en- abling the teletext transcoding will be available. the start and stop times of this window can be programmed between lines 6 and 22 (319 and 335) to span all teletext lines in the pal standard. for proper synchronization the mac sync signal from the d2mac decoder will be used. 2.7. osd formatter and insertion an external on-screen signal (e.g. from the tpu 2735) can be fed into the dmi. the signal is 3 1 bit rgb and fast blanking. these input signals are sampled with the double clock frequency and processed with a downsam- pling filter to the single clock frequency. in the osd for- matter the 3-bit rgb signals are converted to yuv com- ponent signals, 6 bit for y, 5 bit for u and 5 bit for v. this is done in a user-programmable ram with a size of 8 16 bit. contrast, brightness and saturation of the osd can be programmed in this way. the output signal of the osd formatter is fed into the pal encoder and into the rgb/yuv outputs. the osd can be switched off separately for pal and rgb/yuv. 2.8. luminance offset subtracter the digital luminance signal coming from the d2mac decoder has an offset of 16. this means that the black level is shifted to this value. at the luminance input of the dmi 3110 a a value of 16 can be subtracted from the lu- minance signal. therefore, the range of the luminance signal is from 0 to 238. the d/a output range is set to 0.75 v for full-scale (255) input, hence the amplitude of 238 gives 0.7 v at the output. 2.9. equalization delay the pal encoder has a processing delay of some micro- seconds. for a time matching between the analog rgb signals and the y, c and cvbs signals an equalization delay exists. this delay is adjustable because the en- coder delay depends on the filter settings.
dmi 3110 a micronas intermetall 6 2.10. 4:4:4 interpolation the component signal from the d2mac decoder is in 4:2:2 format. before this signal is converted to rgb, the u and v components are upsampled to the full clock fre- quency of 20.25 mhz. this is done by demultiplexing the u and v signals and by interpolation of the signal with a fir filter. the frequency response and step response are shown in fig. 22. 2.11. matrix a digital matrix converts the 4:4:4 yuv signal to a rgb signal. the matrix can be switched off for outputting yuv signals. the matrix coefficients are fixed and have the following values: r y 0 u 1.079 v g y 0.265 u 0.549 v b y 1.364 u 0 v 2.12. d/a converters there are six d/a converters in the dmi. three of them output the rgb or yuv signals, one is for the composite video signal, one for the chrominance signal and one for the luminance signal. the signal delay time of all con- verters is matched. the minimum load resistor for the nominal output voltages is 75 w .the converters consist of current sources from the analog supply voltage vsupa. with a digital zero input all current sources are switched to ground and the maximal current flows inter- nally. in this case the d/a converters have the maximal power dissipation. at maximal input signal all current sources are switched to the output pin and the current flows over the external load resistor to ground. the out- puts are short-circuit protected. the maximal output currents can be adjusted in a range from 25% to 100% of the values in the table below. the adjustment is done with two reference resistors. one of them is responsible for the rbg converters, the other one for the y, c and cvbs converters. at 25% of the cur- rent the load resistance has to be 300 w to get the correct output voltage. the output voltage should not exceed a value of approx. 1.4 v because at higher values the d/a converter characteristic becomes nonlinear. if all six d/a converters are used, the load resistance has to be 300 w in order to not exceed the maximum power dissipation of 1.325 w for the existing package. for lower load resistances (higher power dissipation) the package has to be cooled. for a lower power dissipation the unused group of d/a converters can be switched off by removing the corre- sponding reference resistor. table 21: specifications of the d/a converters signal resolu- tion max. current v outmax at 75 w cvbs 9-bit 16.5 ma 1.24 v luma 9-bit 16.5 ma 1.24 v (1 v nominal) chroma 9-bit 16.5 ma 1.24 v (0.8 v pp nominal) r, g, b 8-bit 10.0 ma 0.75 v 2.13. i 2 c-bus interface all parameters of the dmi 3110 a are programmed via an i 2 c-bus interface. the interface uses an ic address and one level of subaddress. the programming of the dmi 3110 is explained in detail in section 4. fig. 22: 422 444 chroma interpolation filter
dmi 3110 a micronas intermetall 7 10 11 12 13 14 15 16 17 18 19 20 1 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 59 60 61 62 63 64 65 66 67 68 58 2 3 4 5 6 7 8 9 dmi 3110 a 10 11 12 13 14 15 16 17 18 19 20 1 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 59 60 61 62 63 64 65 66 67 58 2 3 4 5 6 7 8 9 dma 2381 v0 v1 v2 v3 v4 v5 v6 v7 c0 c1 c2 c3 c4 c5 c6 c7 v0 v1 v2 v3 v4 v5 v6 v7 c0 c1 c2 c3 c4 c5 c6 c7 l0 l1 l2 l3 l4 l5 l6 l7 l0 l1 l2 l3 l4 l5 l6 l7 18.432 mhz 64k x 1 dram a0 a1 a2 a3 a4 a5 a6 a7 a0 a1 a2 a3 a4 a5 a6 a7 1 2 3 4 5 6 7 8 9 10111213141516 68 rdio r/w ras cas + 5v imc imd imi im bus clock data ident reset plld pllc pllc plld clmp clmp + 5v sbc sbd aclk sbi mclk mclk csync csync + 5v 2 x 3.9 pf 20.25 mhz mdat msync r g b fb on screen display red green blue fast bdat bsync clock data sda scl + 5v analog 100p 47p 10 m 6.8p 33k 330 1k 2.7k bc848 bc858 1n 4148 iic bus blank 0.1 m 0.1 m 0.1 m 5k 5k 470 330 100p 47p 10 m 6.8p 33k 330 1k 2.7k bc848 bc858 1n 4148 100p 47p 10 m 6.8p 33k 330 1k 2.7k bc848 bc858 1n 4148 100p 47p 10 m 6.8p 33k 330 1k 2.7k bc848 bc858 1n 4148 100p 47p 10 m 6.8p 33k 330 1k 2.7k bc848 bc858 1n 4148 100p 47p 10 m 6.8p 33k 330 1k 2.7k bc848 bc858 1n 4148 + 5v analog + 5v analog + 5v analog + 5v analog + 5v analog + 5v analog red green blue luminance composite video chrominance = digital ground = analog ground mac input 1 mac input 2 0.47 m 0.47 m 75 75 fig. 23: application circuit
dmi 3110 a micronas intermetall 8 3. specifications 3.1. outline dimensions fig. 31: 68-pin plastic leaded chip carrier package (plcc68 ) weight approximately 4.8 g dimensions in mm 1.2 x 45 16 x 1.27 = 20.32 0.1 0.1 24.2 0.1 2 25 +0.25 43 27 25 +0.25 26 10 9 61 9 44 60 1 x 45 0.457 0.2 0.711 1.9 1.5 4.05 0.1 4.75 0.15 1.27 0.1 2.4 2 15 9 1.27 0.1 16 x 1.27 = 20.32 0.1 0.1 24.2 0.1 1 +0.2 2.4 70043/2 3.2. pin connections and short descriptions nc not connected; leave vacant lv if not used, leave vacant x obligatory, connect as described in circuit diagram pinno. connection pin name type short description plcc 68-pin (if not used) 1 lv bo5 out digital baseband output 5 2 lv bo6 out digital baseband output 6 3 lv bo7 out digital baseband output 7 (msb) 4 x vsupd sup digital supply voltage 5 x gndd sup digital ground 6 gndd clmp in clamping input 7 lv mclk out main clock output 8 gndd li7 in digital luma input 7 (msb) 9 gndd li6 in digital luma input 6 10 gndd li5 in digital luma input 5 11 gndd li4 in digital luma input 4 12 gndd li3 in digital luma input 3 13 gndd li2 in digital luma input 2
dmi 3110 a micronas intermetall 9 pin connections and short descriptions, continued pin connection pin name type short description no. (if not used) 14 gndd li1 in digital luma input 1 15 gndd li0 in digital luma input 0 (lsb) 16 gndd ci0 in digital chroma input 0 (lsb) 17 gndd ci1 in digital chroma input 1 18 gndd ci2 in digital chroma input 2 19 gndd ci3 in digital chroma input 3 20 gndd pllc in pll tuning clock input 21 gndd plld in pll tuning data input 22 gndd ci4 in digital chroma input 4 23 gndd ci5 in digital chroma input 5 24 gndd ci6 in digital chroma input 6 25 gndd ci7 in digital chroma input 7 (msb) 26 x resq in reset input 27 x xtal1 out crystal 1 (output) 28 x xtal2 in crystal 2 (input) 29 vsupd csync in composite sync input 30 gndd mdat in mac data input 31 vsupd msync in mac sync input 32 x tmode in test mode 1 33 x tlat in test mode 2 34 gnd osdr in on-screen display red input 35 gnd osdg in on-screen display green input 36 gnd osdb in on-screen display blue input 37 gnd osdfb in on-screen display fast blank input 38 x testop1 out test mode 3 39 x testop2 out test mode 4 40 x ckmode in test mode 5 41 x tckin in test mode 6 42 x not connected 43 x gndcon supply ground connection 44 gndda rout out analog red or v-component output
dmi 3110 a micronas intermetall 10 pin connections and short descriptions, continued pin connection pin name type short description no. (if not used) 45 x rrefr ref reference r for rgb dacs 46 gndda gout out analog green or luminance output 47 x gndda supply analog ground d/a converters 48 gndda bout out analog blue or u-component output 49 x vsupda supply analog supply voltage dacs 50 gndda yout out analog luminance output 51 x crefda ref reference capacitor for dacs 52 gndda cvbsout out analog composite video output 53 x rrefy ref reference r for y, c, cvbs dacs 54 gndda cout out analog chrominance output 55 x gndad supply analog ground a/d converters 56 x vsupad supply analog supply voltage adc 57 x vreft ref top reference voltage adc 58 vreft mac2 in mac input 2 59 x gndsig in signal ground adc 60 vreft mac1 in mac input 1 61 x gndsub supply substrate voltage 62 x sda in/out i 2 c-bus serial data input/output 63 x scl in i 2 c-bus serial clock input 64 lv bo0 out digital baseband output 0 (lsb) 65 lv bo1 out digital baseband output 1 66 lv bo2 out digital baseband output 2 67 lv bo3 out digital baseband output 3 68 lv bo4 out digital baseband output 4
dmi 3110 a micronas intermetall 11 3.3. pin descriptions pin 1 to 3 and 64 to 68 digital baseband outputs (interface to dma, see fig. 3-9): via these pins the dma circuits will be supplied with the digitized mac baseband signal. the code of the signal is 8-bit pure binary. pin 4 digital supply voltage: this pin supplies all digital stages and has to be con- nected with the positive supply voltage. pin 5 digital ground: this is the common ground connection of all digital stages and has to be connected with the ground of the power supply. pin 6 clamping input (interface to dma, fig. 33): to this pin the dma supplies a pdm (pulse density mod- ulated) signal for clamping the analog mac baseband signal at the input of the agc amplifier. this pin has to be connected to pin 48 of the dma circuit. pin 7 main clock output (supply of dma and others, fig. 310): this pin is the output of the main clock generator. the clock generator drives all circuits with the synchronized clock signal. the clock frequency is 20.25 mhz. pin 8 to 15 digital luma inputs (interface to dma, fig. 32): via these pins the dmi gets the digital luminance signal in 8-bit pure binary code from the dma circuit. all bits equal to zero means black, all bits equal to one means white. pins 16 to 19 and 22 to 25 digital chroma inputs (inter- face to dma, fig. 32): via these pins the dmi gets the digital chrominance sig- nal from the dma circuit. the code is 8-bit two's comple- ment. the components u and v are multiplexed, which means that the data rate of each component signal is 10.125 mhz. pin 20 pll tuning clock input (interface to dma, see fig. 33): this pin gets the clock for the pll tuning data signal from the dma. this pin has to be connected with the pin 26 of the dma circuit. pin 21 pll tuning data input (interface to dma, fig. 33): this pin gets the data signal for the clock generation pll from the dma. the signal is a 12-bit serial data word which will be loaded into a shift register. the data con- tains the information for the frequency adjustment of the clock generator. the data format is compatible with the mcu 2600 clock generator. the clock phase will be compared with the phase of the mac signal clock in the dma circuit. this pin has to be connected with pin 25 of the dma circuit. pin 26 reset input (fig. 34): a low signal at this pin generates a reset. the low-high transition of this signal should come when the supply voltage is stable (power-on reset). the input has schmitt trigger characteristics. pin 27 and 28 xtal 1/2 (fig. 38): the 20.25 mhz crystal is connected with these two pins. pin 27 is the input and pin 28 is the output of the oscillator circuit. both pins need an external capacitor to ground. pin 29 composite sync input (interface to dma, fig. 32): this pin gets the composite sync signal from the dma. this signal is used as synchronization signal in the pal coder of the dmi and has to be connected to pin 53 of the dma circuit. pins 30 and 31 mac data and sync input (interface to dma, fig. 33): via this pin the vbi teletext signal will be supplied from the dma. the burst data signal contains the binary tele- text data in lines 2 to 22 and lines 314 to 334 of the d2mac signal. the burst sync signal synchronizes the teletext data. pin 30 has to be connected to pin 59 and pin 31 has to be connected to pin 58 of the dma circuit. pins 32, 33, 38 to 41 test pins: these pins are for test purposes only. in normal opera- tion the pins 32, 33, 40, and 41 have to be connected to ground. pins 34 to 37 on-screen display inputs (fig. 33): via these pins the dmi will be supplied with the on- screen signals. three inputs are for the one-bit rgb sig- nals, the fourth input is for the fast blanking signal. a high level at the fast blanking input enables the osd signal. this can be inserted (switchable) into all analog output signals of the dmi. the input signals are sampled with twice the clock frequency (40.5 mhz). pin 43 ground connection: this pin has some internal shielding function. it has to be connected to ground. pin 44, 46, 48, 50, 52, 54 analog outputs (fig. 35): these are the outputs of the six d/a converters. the d/a converters are current source types and deliver output currents from vsupa to ground. the nominal output voltages require 75 w load resistances. at higher load resistances the output voltages will increase, but will be- come nonlinear above approx. 2 v. the outputs are short-circuit protected. pin 45 and 53 reference resistors d/a converters (fig. 36): the reference currents for the d/a converters can be ad- justed with a resistor from each of these pins to ground. with these resistors the output currents can be adjusted in the range of 25% to 100% of the maximal output cur- rents. one resistor is responsible for the rgb d/a con- verters, the other one for the y,c,cvbs d/a converters.
dmi 3110 a micronas intermetall 12 the nominal reference resistance value for a given load resistance can be seen in the table arecommended oper- ating conditionso. pin 47 and 55 analog ground: these are the ground pins for the a/d and the d/a con- verters and have to be connected to the ground of the power supply. note: the layout of the printing circuit board should take into consideration the need for a rela- tively noise-free supply. pin 49 and 56 analog supply voltage: these are the supply voltage pins for the a/d and the d/a converters and have to be connected to the positive supply voltage. note: the layout of the printing circuit board should take into consideration the need for a rela- tively noise-free supply. pin 51 reference capacitor d/a converters (fig. 36): this pin is the internal reference for the d/a converters. it has to be connected to ground over a capacitor with a value of approx. 100 nf. the capacitor should be a type with a low inductance and a high insulation resistance. pin 57 top reference voltage a/d converter (fig. 37): this pin is connected to the top end of the reference re- sistor chain of the a/d converter. the reference voltage is generated inside the dmi, therefore only a capacitor has to be connected to this pin. the cold end of the ca- pacitor should be connected to the signal ground. pin 58 and 60 mac inputs (fig. 33): these are the inputs of the a/d converter (respectively clamping circuit) and have to be supplied with the analog mac signals. one of these inputs can be selected via i 2 c-bus. the signal amplitude is nominal 1 v pp and can vary by 6 db. the input signals must be ac-coupled over a capacitor. the clamping time constant is propor- tional to the capacity. pin 59 signal ground a/d converter (fig. 37): this pin has to be connected to the ground of the analog input signal. the layout of the printing circuit board should take into consideration the need for a relatively noise-free signal ground potential. pin 61 substrate voltage: this is the connection to the substrate (platform) of the ic. it has to be connected to ground. pin 62 and 63 i 2 c-bus serial clock and data (fig. 33): these are the connections of the dmi with the i 2 c-bus. all adjustments are done via this bus and the information will be provided by a central control unit (ccu). 3.4. pin configuration 7 8 9 10 11 12 13 14 15 16 17 29 30 31 32 33 34 35 36 37 38 39 18 19 20 21 22 23 24 25 26 27 28 654321 44 43 42 41 40 68 67 66 65 64 63 62 61 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 vsup gnd x2 x1 standby dat_im2 id_im2 clk_im2 timer1 timer2 timer3 ir p10 (d0) p11 (d1) p12 (d2) p13 (d3) p14 (d4) p15 (d5) p16 (d6) p17 (d7) p20 (a0) p21 (a1) p22 (a2) p23 (a3) p24 (a4) p25 (a5) p26 (a6) p27 (a7) p30 (a8) p31 (a9) p32 (a10) p33 (a11) p34 (a12) p35 (a13) p36 (a14) p37 (a15) p50 p51 p52 p53 p54 p55 p70 p71 p72 p73 p74 p75 p76 p77 p80 p81 p82 p83 p87/int p60 p61 p62 p63 p64 p65 p66 p67 dmi 3110 a res dat _ im1 id_im1 clk_im1 p4 (r/w ) v fig. 32: pinning of the dmi 3110 a in plcc68 package
dmi 3110 a micronas intermetall 13 3.5. pin circuits p n gnd v sup fig. 33: input pins 8 to 19, 22 to 25, 29 v sup p n gnd fig. 34: input pins 6, 20, 21, 30, 31, 34 to 37, 53, 60, 62, 63 n p p p n n v sup gnd fig. 35: input pin 26 p v sup fig. 36: output pins 44, 46, 48, 50, 52, 54 int. ref. voltage ref. current vsupa gnda fig. 37: pins 45, 51, 53 51 45, 53 + vsupa 350 w gndsig vreft p ~ fig. 38: pins 57, 59 int. ref. voltage v sup gnd p n p n 0.5 m 27 28 fig. 39: input pin 27, output pin 28 p n bias bias p n v sup gnd fig. 310: output pins 1 to 3, 64 to 68 v sup n p gnd fig. 311: output pin 7
dmi 3110 a micronas intermetall 14 3.6. electrical characteristics (pin numbers for 68-pin plcc package) 3.6.1. absolute maximum ratings symbol parameter pin no. min. max. unit t a ambient operating temperature 0 65 c t s storage temperature 40 125 c v sup supply voltage 4, 49, 56 6 v v i input voltage, all pins 0.3 v sup v i i input current, all pins 20 20 ma p tot chip power dissipation 1.325 w stresses beyond those listed in the aabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions beyond those indicated in the arecommended operating conditions/characteristicso of this specification is not implied. exposure to absolute maxi- mum ratings conditions for extended periods may affect device reliability. 3.6.2. recommended operating conditions at v sup = 5 v, t a = 0 c to 65 c symbol parameter pin no. min. typ. max. unit v supd digital supply voltage 4 4.75 5.0 5.25 v v supa analog supply voltage 49, 56 4.75 5.0 5.25 v v mac analog mac input voltage 58, 60 0.5 1.0 2.0 v ss c maci coupling capacitance mac inputs 470 nf c reft decoupling capacitance top reference a/d converter 57 10||10 nf|| m f c refd decoupling capacitance a/d converter 51 100 nf r refr reference resistor rgb d/a converter 45 1100 4400 w r refy reference resistor, y, c, cvbs d/a converter 53 680 2720 w r load load resistance d/a converter 44, 46, 48 50 0 75 300 w v amax maximum output voltage range (all d/a converters) 48, 50, 52, 54 1.4 v v lcil digital luma/chroma input low voltage 8 to 19, 22 to 25 0.4 v v lcih digital luma/chroma input high voltage 2.4 v t lcist digital luma/chroma input setup time 10 ns t lciht digital luma/chroma input hold time 0 ns
dmi 3110 a micronas intermetall 15 recommended operating conditions, continued symbol parameter pin no. min. typ. max. unit v osdl osd input low voltage 34 to 37 0.2 v v osdh osd input high voltage 0.6 v t osdsl osd input setup time at falling clock edge 10 ns t osdhl osd input hold time at falling clock edge 0 ns t osdsh osd input setup time at rising clock edge 10 ns t osdhh osd input hold time at rising clock edge 0 ns v reil reset input low voltage 26 0.8 v v reih reset input high voltage 2.8 v t reil reset input low time 1 m s v iic i 2 c-bus input low voltage 62, 63 1.5 v v iic i 2 c-bus input high voltage 62, 63 3.0 v 3.6.3. crystal oscillator (dco) characteristics (for tc09) symbol parameter min. typ. max. unit recommended crystal characteristics t a operating ambient temperature 0 65 c f p parallel resonance frequency with load capacitance c l = 13 pf 20.250 mhz d f p /f p accuracy of adjustment 20 +20 ppm d f p /f p frequency temperature drift 30 +30 ppm r r series resistance 25 w c 0 shunt (parallel) capacitance 3 7 pf c 1 motional (dynamic) capacitance 20 ff load capacitance recommendation c l external load capacitance 1) from pins 27 and 28 to ground (pin names: xtal_in, xtal_out) 2.2 pf dco characteristics c ilmin minimum effective load capacity 2) 9.5 pf c ilrng effective load capacity range 2) 7.5 pf 1) remark on defining the external load capacitance: external capacitors at each crystal pin to ground are required. they are necessary to tune the open-loop frequency of the in- ternal pll and to stabilize the frequency in closed-loop operation. the higher the capacitors, the lower the clock frequency results. the nominal free running frequency should match 20.250 mhz as closely as possible. due to different layouts of cus- gq y y y tomer pcbs the matching capacitor size should be defined in the application. the suggested value is a figure based on expe- rience with various pcb layouts. tuning condition: vcoa = 25 (bits 7...0 of im-bus register 14 of dma 2281/dma 2381) 2) dco range 128...384
dmi 3110 a micronas intermetall 16 3.6.4. characteristics at v sup = 5 v, t a= 0 to 65 c symbol parameter pin no. min. typ. max. unit test conditions i supd current consumption digital 4 130 160 ma v supd 5.0 v i supaf current consumption analog front-end 56 50 70 ma v supaf 5.0 v i supab current consumption analog back-end 49 30 35 ma v supab 5.0 v r refy 2720 w r refr 4400 w r load 6 300 w 110 1) 130 1) ma v supab 5.0 v r refy 680 w r refr 1100 w r load 6 75 w p tot total power dissipation 1050 1325 mw v supab 5.0 v r refy 2720 w r refr 4400 w r load 6 300 w 1450 1) 1800 1) mw v supab 5.0 v r refy 680 w r refr 1100 w r load 6 75 w front-end v reft a/d converter top reference voltage 57 2.55 2.7 2.85 v r mac analog input impedance 58, 60 1 m w c mac analog input capacitance 5 pf i clmp analog input clamping current range +14 12 +17 15 +20 18 m a m a full range, divided into 17 steps of 2 m a offset +1 m a v mac mac input voltage full range 0.9 1.0 1.1 v pp agc= 0db (code 32) g mac agc range in: 58, 60 6 7 8 db full range divided into 64 steps dn agc agc differential nonlinearity out: 13 0.8 lsb b mac frontend 3 db bandwidth at 100 % signal 1 ... 3 , 64...68 7.5 8 mhz f mclk 20.25 mhz agc= 6 db (code 0) snd mac frontend signal to noise and distortion ratio at 100 % signal 42 44 db 1 mhz sine input agc= 6 db (code 0) bandwidth fs/2 thd mac total harmonic distortion at 100 % signal 42 48 db 1 mhz sine input agc= 6 db (code 0) bandwidth 6 mhz psrr mac power supply rejection ratio at mac input 46 db d v supad / d v mac at dc agc= 0 db (code 32) in mac mac input integral non- linearity 2 lsb dn mac mac input differential non- linearity 0.8 lsb ct mac analog input adjacent cross- talk mac1/mac2 55 50 db input1 1 mhz 80 % signal input2 1.1 mhz 80 % signal 1) cooling required.
dmi 3110 a micronas intermetall 17 characteristics, continued symbol parameter pin no. min. typ. max. unit test conditions back-end v ref reference voltage for all d/a converters 51 1.9 2.1 2.3 v v supa 4.75 to 5.25 v to be measured with r j 1 g w i outy maximum analog output current cvbs, y, c 50, 52, 54 15.6 16.5 17.3 ma r refy 680 w r l 0 4.1 ma r refy 2720 w r l 0 i outr maximum analog output current r, g, b 44, 46, 48 9.5 10 11 ma r refr 1100 w r l 0 2.5 ma r refr 4400 w r l 0 id outr output deviation between r, g and b peaktopeak current 3 6 % 100(i max i min )/i mean r refr 1100 w r l 0 dn dac differential nonlinearity (all d/a converters) 44, 46, 48, 50, 52 54 0.3 lsb in dac integral nonlinearity (all d/a converters) 52 , 54 0.5 lsb thd dac total harmonic distortion (all d/a converters) 50 db signal 1mhz bandwidth 6 mhz miscellaneous v mclkd clock output dc voltage 7 2.5 v c l 50 pf v mclca clock output voltage swing 1.0 1.2 1.4 v pp c l 50 pf t mclkr clock rise time 9 ns c l 50 pf t mclkf clock fall time 11 ns c l 50 pf r mclk clock output impedance 30 w ac coupling v lcit digital luma/chroma input threshold voltage 8 to 19, 22 to 25 1.1 v i lcil digital luma/chroma input low current 1.4 2.0 3.0 ma v il 0.4 v c lci digital luma/chroma input capacitance 5 pf v osdt osd input threshold voltage 34 to 37 0.4 v i osdl osd input leakage current 1 m a c osd osd input capacitance 5 pf v resqt reset input threshold voltage 26 2.2 v rising edge i resql reset input low current 1.2 v falling edge i resqh reset input high current 0 m a c resq reset input capacitance 5 pf
dmi 3110 a micronas intermetall 18 characteristics, continued symbol parameter pin no. min. typ. max. unit test conditions v bol digital baseband output low voltage 1 to 3, 64 to 68 2.2 v v boh digital baseband output high voltage 2.8 v t bod digital baseband output delay time 16.5 ns c l 50 pf i iicil i 2 c-bus input leakage current 62, 63 1 m a c iici i 2 c-bus input capacitance 5 pf v iicol i 2 c-bus output low voltage 62 0.4 v i low 3.0 ma fig. 312: data input & outputs timing chart and symbols thi1 ts1 clock (mclk) data outputs data inputs note : all digital luma and chroma inputs use ts1 and thi1; ts2 and thi2 are used for pll clock/ data, csync and msync/mdata both edges are used for the double clock osd input thi2 ts2 td tho
dmi 3110 a micronas intermetall 19 4. programming 4.1. i 2 c-bus interface the i 2 c-bus interface is used to program all parameters to the dmi 3110 a. data can only be written to the dmi 3110 a. the i 2 c-bus interface uses a chip address, a register (sub-) address and an 8-bit data word that is written to the addressed register. the bus protocol is shown in the figure below. the main address is $0e. the register assignment for the i 2 c-bus registers is giv- en in the following table. the dmi 3110 a evaluation soft- ware allows the access of all subregisters via the indi- cated mnemonics. (msb first) r/w s ack p ack subaddress 000 1110 sda scl 1 0 sp data byte ack r/w =0 ack = 0 fig. 41: i 2 c-bus protocol
dmi 3110 a micronas intermetall 20 table 41: i 2 c-bus registers i 2 c subad- dress i 2 c data[7:0] name default 0 not used 0 1 d[7:0] timing generator disable time tgdis 250 2 d[7] reserved d[6] low pass filter on d[5:0] luma gain adjustment ylpf ygain 0 0 24 3 d[4:0] chroma gain adjustment cgain 22 4 d[7:0] pal color burst amplitude burst 40 5 d[7] reserved d[6] chroma demultiplexer phase (pal) d[5:2] chroma peaking filter d[1] chroma lowpass filter (f2) d[0] chroma lowpass filter (f1) palmux clppk clpf2 clpf1 0 0 8 1 1 6 d[7] reserved d[6:0] b-y gain ugain 0 63 7 d[7] reserved d[6:0] r-y gain vgain 0 90 8 d[7:0] luminance blanking start yblanks 2 9 d[7:0] luminance blanking end yblanke 100 10 d[7:0] key pulse start keys 73 11 d[7:0] key pulse end keye 97 12 d[7:4] vertical blanking length d[3:0] reserved vblen 10 0 13 d[7:6] reserved d[5:0] luminance delay ydel 0 42 14 d[7:4] reserved d[3:0] composite sync delay csdel 0 4 15 d[7] reserved d[6:4] testbits d[3] special sync mode d[2] osd-insertion into pal enable d[1:0] testbits palosd 0 0 0 0 0 16 testregister d[7:6] testbits d[5] ttx-insertion disable d[4:2] testbits d[1] sync pulse output disable d[0] reserved 0 0 0 0 0 17 d[7:0] chroma blanking start cblanks 13 18 d[7:0] vertical sync trigger point vstrig 50 19 d[7:0] chroma blanking end cblanke 111
dmi 3110 a micronas intermetall 21 i 2 c-bus registers , continued i 2 c subad- dress i 2 c data[7:0] name default 20 d[7:0] horizontal sync start hsyncs 0 21 d[7:0] horizontal sync end hsynce 1 22 testregister d[7:6] testbits d[5] b-y disable d[4] r-y disable d[3:0] testbits 0 0 0 0 23 d[7:0] ttxinsertion start ttxs 116 2425 reserved 26 d[7] reserved d[6] chroma demultiplexer phase (rgb) d[5] osd-insertion into rgb(yuv) enable d[4] luma offset subtracter control d[3] interpolation filter bypass d[2] rgb-matrix bypass d[1:0] testbits rgbmux rgbosd yoffset rgbfbp rgbmbp 0 0 0 0 0 0 0 27 d[7:4] reserved d[3:0] rgb (yuv)-delay rgbdel 0 12 28 not used 29 testregister d[7:0] testbits 0 30 d[6:0] ttx-window 2 end (line 256 x) ttxw2e 79 31 d[7] testbit d[6:0] ttx-window 2 start (line 256 x) ttxw2s 0 62 32 d[6:0] ttx-window 1 end ttxw1e 23 33 d[7] start sample ttx read 230/231 (1/0) d[6:0] ttx-window 1 start ttxss ttxw1s 0 6 34 d[7:6] reserved d[5] gray code off d[4] input select d[3:2] testbits d[1] clamping enable d[0] reserved grayoff macin clampen 0 0 1 0 1 0 35 testregister d[7] adc-standby control d[6] gray code test control d[5:0] testbits 0 0 0 36 d[5:0] automatic gain control agc 25 37 to 47 not used 48 to 63 d[7:0] osd color look-up table osdx
dmi 3110 a micronas intermetall 22 table 42: related dma 2281 im-bus registers im-bus address im-bus data[15:0] name default 23 d[15:10] saturation u sau 32 23 d[7:2] saturation v sav 32 200 d[15:10] luma contrast ct 63 200 d[8] luma contrast switch cts 1 202 d[15:9] composite sync delay sd 70 4.2. general remarks for an easy adjustment of the dmi 3110 a, the mubi software can be used. the parameter names mentioned below refer to the mubi software and are in the same or- der. the register subaddress is always given in paren- thesis. 4.2.1. initialization command name: init or [f10] this is a command in the mubi program. it initializes the dmi 3110 a with the parameters set to the most recent values. before this command, a hardware reset (power- on reset) should be done. 4.3. analog input 4.3.1. input select (34) command name: macin this command switches between the analog mac in- puts 1 and 2. macin 1 means the mac input 1 is se- lected. macin 0: input 2 (pin 60) 1: input 1 (pin 58) 4.3.2. clamping enable (34) command name: clampen this command enables the clamping at the analog mac inputs. clampen 1 means that the clamping is en- abled. clampen 0: clamping disabled 1: clamping enabled 4.3.3. automatic gain control (36) command name: agc the agc value controls the gain of the input amplifier. in normal operation the ccu reads the amplitude value out of the dma and adjusts the agc value in the dmi for a proper signal amplitude at the a/d converter. the range of 6 db is divided into 64 steps. agc value gain[db] / 0.19 db range 0 to 63 4.3.4. baseband output code (34) command name: gray the digital baseband output code of the dmi 3110 a can be switched over between straight binary code and gray code. grayoff 1: binary code 0: gray code 4.4. chrominance channel 4.4.1. chroma demultiplexer phase (5, 26) palmux rgbmux 0: normal 1: inverted
dmi 3110 a micronas intermetall 23 4.4.2. chroma lowpass (5) command names: clpf1, clpf2, clppk this filter consists of 1 fixed part and 3 adjustable parts in series. parts 1 to 3 are lowpass filters, part 4 is an ad- justable peaking filter. the transfer functions are: table 43: transfer functions part 1 fixed h(z) 0.5 (1 z 4 ) (1 z 2 ) 2 part 2 f1 0 h(z) 0.5 (1 z 4 ) clpf1 f1 1 h(z) z 4 part 3 f2 0 h(z) 0.5 (1 z 6 ) clpf2 f2 1 h(z) z 6 part 4 pk 1 h(z) z 6 4/16 (1 z 12 ) clppk pk 2 h(z) z 6 3/16 (1 z 12 ) pk 4 h(z) z 6 2/16 (1 z 12 ) pk 8 h(z) z 6 1/16 (1 z 12 ) 4.4.3. color component gain (6,7) command names: ugain, vgain this is the gain adjustment for the color component sig- nals in front of the 4:4:4 interpolation filter (after the low- pass filter). the by signal is multiplied with the ugain value to result in the u component signal. the ry sig- nal is multiplied with the vgain value to result in the v component signal. the gain should be adjusted as high as possible (short before signal limitation) for a low quantization noise. ugain value 128 gain range 0 to 127 vgain value 128 gain range 0 to 127 4.4.4. color burst (4) command name: burst this is the value of the burst amplitude. the adjustment is relative to a maximum chroma amplitude of 1. this val- ue's sign has to be negative. the positive sign can be used for test purposes. the formula for the calculation is: value = 91 burst amplitude range 128 to 127 4.4.5. color carrier gain (3) command name: cgain the gain for the color subcarrier can be adjusted in front of the d/a converter (after the pal modulator). this ad- justment influences the color carrier inclusive the burst. the formulae for the calculation of these values are: cgain value 32 gain range 0 to 31 4.5. luminance channel 4.5.1. luminance offset (26) command name: yoffset a luminance offset can be added at the luminance input. the offset will be added in the rgb as well as the pal coder path. yoffset 0 offset 16 1 offset 0 4.5.2. luminance lowpass filter (2) command name: ylpf in the luma path of the encoder a switchable low-pass filter with a transfer function 1+z 1 can be selected. ylpf 0: bypass 1: lowpass 0.5 (1 z 1 ) 4.5.3. luminance gain (2) command name: ygain the luminance gain for the luminance signal at the com- posite video output can be adjusted after the chroma trap. the formula for the calculation of this value is: ygain value 64 gain range 0 to 63
dmi 3110 a micronas intermetall 24 4.6. timing 4.6.1. horizontal pulses (1, 8 to 11, 17, 19) command names: tgdis, keys, e, yblanks, e, cblanks, e all these pulses are started with the low transition of the hsync in the composite sync signal. the end of the tim- ing generator (tgdis) stops the pulse generation. it must therefore have the highest value of all. while the timing generator is running, the trigger input is disabled. this is necessary to prevent the timing generator from triggering at the h/2 pulses (equalization pulses) in the vertical sync signal. all pulses, except timing generator are adjustable within a step width of two clock periods, and have a range of 2 to 510 clock periods. the timing generator has a range of 4 to 1020 clock periods. tgdis value t delay f clock / 4 range 1 to 255 key value t delay f clock / 2 range 1 to 255 yblank value t delay f clock / 2 range 1 to 255 cblank value t delay f clock / 2 range 1 to 255 4.6.2. short vertical sync (15, 20, 21) command names: ssync, hsyncs, e it is possible to replace the vertical sync signal with a special short vertical sync signal with a duration of one horizontal line. the position of this sync pulse is one line before the original vertical sync pulse would appear. this mode can be selected with the ssync command. in this mode the composite sync signal is switched off and the short vertical sync pulse is used. the horizontal sync pulses are generated from the timing generator. therefore the start and end values for the hsync have to be adjusted. ssync 0: composite sync 1: short vertical sync hsync value t delay f clock / 2 range 1 to 255 4.6.3. vertical pulses (12, 18) command names: vstrig, vblen the detection level for the vertical sync separator can be adjusted to start the generated vertical blanking at the start of the equalization pulses or at the start of vertical sync pulses. a counter which runs with fc/8 starts at each rising edge of the composite sync signal. at the fal- ling edge the counted number is compared with the detection level vstrig. if the counted number is small- er than the detection level a vertical blanking pulse will be generated. the duration of the vertical blanking pulse (vblen) can be adjusted between 0 and 15. vstrig value f c t high / 8 range 0 to 255 vblen value n h range 0 to 15 example for vstrig: fc 20.25 mhz high time at normal line 59.3 m s 20.25 mhz / 8 150 high time at equal. pulses 29.7 m s 20.25 mhz / 8 75 high time at vsync pulses 4.7 m s 20.25 mhz / 8 12 for a start of the vertical blanking at the equalization pulses the detection level has to be between 75 and 150. for a start of the vertical blanking at the vsync pulses the detection level has to be between 12 and 75. 4.6.4. delay for csync, luminance and rgb (13, 14, 27) command names: csdel, ydel, rgbdel the delays for the composite sync, the luminance signal and the rgb signals can be adjusted separately. the lu- minance delay has to be adjusted for matching with the chroma signal. the rgb delay has to be adjusted for matching with the composite video signal. csdel value (see *) range 0 to 15* ydel value t delay f clock range 0 to 63 rgbdel value t delay f clock range 0 to 15 * the delay is added to the luma delay and the weighting of the bits is not binary weighting: bit 0 1, bit 1 1, bit 2 1, bit 3 2 (maximum delay 5 clock periods).
dmi 3110 a micronas intermetall 25 4.7. teletext transcoder (23, 30 to 33) command names: ttxs, ttxss, ttxw1s, _e, ttxw2s, _e the teletext transcoder allows to select lines from the d2mac/dmac signal for the transcoding function. two blocks of lines can be selected, for each block the first and the last line number must be programmed. if the last line number is smaller than the first line number the transcoding is inactive. the exact time for the insertion of the teletext signal into the luminance and composite signals can be programmed with the value of ttxs.tf. for dmac ttx transcoding, one of the two bit streams can be selected by selecting the start sample point for the ttx transcoder. ttxs value t delay f clock range 0 to 255 ttxss sample at 230 / 231 range 0/1 ttxw1 value n h range 0 to 63 ttxw2 value 256 n h range 0 to 63 4.8. on-screen display (48 to 63) command names: palosd, rgbosd, osdy0...7, osdu0...7, osdv0...7 the osd insertion function can be activated separately for the composite video and svhs signal (encoder) and the rgb path. the on-screen display colors are programmed by a color look up table. for each color (0 to 7) of a binary rgb sig- nal a 16-bit entry in the color look up table allows to pro- gram luminance with 6-bit resolution and chrominance (u/v) with 5-bit resolution respectively. palosd 0: osd disabled into pal 1: osd enabled into pal rgbosd 0: osd disabled into rgb 1: osd enabled into rgb clut[7:0] address: rgb color number data: 2 byte d0[7:2] luma d0[1:0], d1[7:5] chroma (u) d1[4:0] chroma (v) 4.9. rgb processing the component processing path makes it possible to by- pass the 4:2:2 to 4:4:4 interpolation filter and also to by- pass the yuv to rgb matrix. when the matrix is by- passed, the blue/red outputs which carry the u/v data are switched to signed binary format. the u/v mul- tiplex is resynchronized on every line with the mac sync signal; the multiplex order is adjustable. the on-screen display can be enabled to the rgb path. the rbg pro- cessing path has an adjustable delay to match the timing of composite/component signals. rgbfbp 1 : bypass rgbmbp 1 : bypass rgbmux 1: u/v multiplex inverted
dmi 3110 a micronas intermetall 26
dmi 3110 a micronas intermetall 27
dmi 3110 a micronas intermetall 28 5. data sheet history 1. data sheet: admi 3110 a digital mac interfaceo, july 1, 1996, 6251-381-1ds. first release of the data sheet. micronas intermetall gmbh hans-bunte-strasse 19 d-79108 freiburg (germany) p.o. box 840 d-79008 freiburg (germany) tel. +49-761-517-0 fax +49-761-517-2174 e-mail: docservice@intermetall.de internet: http://www.intermetall.de printed in germany order no. 6251-381-2ds all information and data contained in this data sheet are with- out any commitment, are not to be considered as an offer for conclusion of a contract nor shall they be construed as to create any liability. any new issue of this data sheet invalidates previous issues. product availability and delivery dates are ex- clusively subject to our respective order confirmation form; the same applies to orders based on development samples deliv- ered. by this publication, micronas intermetall gmbh does not assume responsibility for patent infringements or other rights of third parties which may result from its use. reprinting is generally permitted, indicating the source. how- ever, our prior consent must be obtained in all cases.

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